SH7261 Datasheet, PDF (796/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Slave transmit mode
Clear AAS in ICSR
Write transmit data
in ICDRT
Read TDRE in ICSR
No
TDRE = 1 ?
Yes
No
Last byte?
Yes
Write transmit data
in ICDRT
Read TEND in ICSR
No
TEND = 1 ?
Yes
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Dummy-read ICDRR
Clear TDRE in ICSR
End
[1] Clear the AAS flag.
[1] _{[2] Set transmit data for ICDRT (except for the last byte).}
[3] Wait for ICDRT empty.
[2]
[4] Set the last byte of transmit data.
[5] Wait for the last byte to be transmitted.
[3]
[6] Clear the TEND flag.
[7] Set slave receive mode.
[8] Dummy-read ICDRR to release the SCL.
[4]
[9] Clear the TDRE flag.
[5]
[6]
[7]
[8]
[9]
Figure 17.20 Sample Flowchart for Slave Transmit Mode
Rev. 2.00 Sep. 07, 2007 Page 764 of 1312
REJ09B0320-0200