SH7261 Datasheet, PDF (656/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
Timing to Change CKS1
No.
and CKS0 Bits
TCNT Clock Operation
4
Switching from high to high
Clock before
switchover
Clock after
switchover
TCNT input
clock
TCNT
N
N+1
N+2
CKS bits changed
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated because the change of the signal levels is considered as a falling edge;
TCNT is incremented.
13.8.7 Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
mode and compare match count mode simultaneously.
13.8.8 Module Standby Setting
Operation of the TMR can be disabled or enabled using the standby control register. The initial
setting is for operation of the TMR to be halted. Register access is enabled by clearing module
standby mode. For details, see section 27, Power-Down Modes.
13.8.9 Interrupts in Module Standby Mode
If module standby mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source. Interrupts should therefore be disabled before entering module
standby mode.
Rev. 2.00 Sep. 07, 2007 Page 624 of 1312
REJ09B0320-0200