SH7261 Datasheet, PDF (380/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.4.2 DMA Transfer Condition
There are three methods of DMA transfer  the unit transfer operation, sequential operand
transfer, and non-stop transfer. These are selectable through the setting of the DMA transfer
condition selection bits (DSEL) in DMA Control Register A (DMCNTAn). Each of the conditions
is explained below. Table 11.5 and figure 11.3 are a list and chart of the DMA transfer conditions.
(1) Unit Operand Transfer
Setting the DMA transfer condition selection bits (DSEL) to 00 selects this mode. A single DMA
request initiates continuous transfer of the number of bytes selected by the OPSEL bits in the
DMA mode register. If the byte counter does not reach 0 in single operand transfer, the DMA
transfer is completed by repeating unit transfer operations until the byte counter does reach 0.
(2) Sequential Operand Transfer
Setting the DMA transfer condition selection bits (DSEL) to 01 selects this mode. A single DMA
request initiates transfer in units of the number of bytes selected by the OPSEL bits in the DMA
mode register (i.e., unit transfer operations) until the DMA transfer is complete (i.e., until the byte
counter reaches zero). Channel arbitration is performed on completion of each unit transfer
operation. Transfer on the channel for the sequential operand transfer automatically resumes
unless there is a DMA request from a higher-priority channel.
(3) Non-Stop Transfer
Setting the DMA transfer condition selection bits (DSEL) to 11 selects this mode. A single DMA
request initiates DMA transfer that continues until the transfer is complete (i.e., until the byte
counter reaches zero). There are no gaps for channel arbitration, so even DMA requests from high-
priority channels will not be accepted.
Rev. 2.00 Sep. 07, 2007 Page 348 of 1312
REJ09B0320-0200