SH7261 Datasheet, PDF (1175/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.3.2 Software Standby Mode
(1) Transition to Software Standby Mode
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit and DEEP bit in STBCR are 1 and 0 respectively. In
software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
The clock output from the CKIO pin also halts in clock mode 0 or 2.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. As for the states of on-chip peripheral module
registers in software standby mode, see section 30.3, Register States in Each Operating Mode.
The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely
reflected in the SLEEP instruction.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
values to secure the specified oscillation settling time.
3. After setting the STBY and DEEP bits in STBCR to 1 and 0 respectively, read STBCR. Then,
execute a SLEEP instruction.
(2) Canceling Software Standby Mode
Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or power-
on reset). In clock modes 0 and 2, a clock signal starts to be output from the CKIO pin.
• Canceling with an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits
(IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC))
is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation
settling counter (WDT) used to count the oscillation settling time.
Rev. 2.00 Sep. 07, 2007 Page 1143 of 1312
REJ09B0320-0200