SH7261 Datasheet, PDF (1080/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 I/O Ports
24.2.1 Register Configuration
Table 24.3 lists the port B registers.
Table 24.3 Register Configuration
Register Name
Port B data register H
Port B data register L
Port B port register H
Port B port register L
Abbreviation R/W
PBDRH
R/W
PBDRL
R/W
PBPRH
R
PBPRL
R
Address
H'FFFE3808
H'FFFE380A
H'FFFE380C
H'FFFE380E
Access Size
8, 16, 32
8, 16
8, 16, 32
8, 16
24.2.2 Port B Data Registers H and L (PBDRH and PBDRL)
PBDRH and PBDRL are 16-bit readable/writable registers that store port B data. Bits PB31DR to
PB0DR correspond to pins PB31 to PB0, respectively.
If a pin is set to the general output function, the pin will output the value written to the
corresponding bit in PBDRH or PBDRL, and the register value is read from PBDRH or PBDRL
regardless of the state of the pin.
If a pin is set to the general input function, the pin state, not the register value, will be returned if
PBDRH or PBDRL is read. Also, if a value is written to PBDRH or PBDRL, although the value
will actually be written, it will have no influence on the state of the pin. Table 24.4 summarizes
the PBDRH and PBDRL read/write operations.
PBDRH and PBDRL are initialized to H'0000 by a power-on reset or in deep standby mode. These
registers are not initialized either by a manual reset or by switching to sleep mode or software
standby mode.
Rev. 2.00 Sep. 07, 2007 Page 1048 of 1312
REJ09B0320-0200