SH7261 Datasheet, PDF (642/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
• TCSR_0
Bit
Bit Name
7
CMFB
6
CMFA
5
OVF
4
ADTE
3, 2
OS[3:2]
Initial
Value
0
0
0
0
00
R/W Description
R/(W)*¹ Compare Match Flag B
[Setting condition]
• When TCNT matches TCORB
[Clearing condition]
• When writing 0 after reading CMFB = 1
R/(W)*¹ Compare Match Flag A
[Setting condition]
• When TCNT matches TCORA
[Clearing condition]
• When writing 0 after reading CMFA = 1
R/(W)*¹ Timer Overflow Flag
[Setting condition]
• When TCNT overflows from H'FF to H'00
[Clearing condition]
• When writing 0 after reading OVF = 1
R/W A/D Trigger Enable
Selects enabling or disabling of A/D converter start
requests by compare match A.
0: A/D converter start requests by compare match A are
disabled
1: A/D converter start requests by compare match A are
enabled
R/W Output Select 3 and 2*²
These bits select a method of TMO pin output when
compare match B of TCORB and TCNT occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B occurs
(toggle output)
Rev. 2.00 Sep. 07, 2007 Page 610 of 1312
REJ09B0320-0200