SH7261 Datasheet, PDF (187/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
F D E EMMM
FDE
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
F: Instruction fetch. Instruction is fetched from memory in which program is stored.
D: Instruction decoding. Fetched instruction is decoded.
E: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
M: Memory access. Memory data access is performed.
Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted
(No Register Banking)
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc + m1
1 Icyc + m1 + 2(m2) + m3
IRQ
m1 m2 m3
m1 m2
First instruction in
interrupt service routine
First instruction in
multiple interrupt service routine
F D E EMMM
FD
D E EMMM
FD
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Interrupt acceptance Multiple interrupt acceptance
Figure 6.5 Example of Pipeline Operation for Multiple Interrupts
(No Register Banking)
Rev. 2.00 Sep. 07, 2007 Page 155 of 1312
REJ09B0320-0200