SH7261 Datasheet, PDF (597/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.17 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 12.123 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
TCFV
H'FFFF
Disabled
H'0000
Figure 12.123 Contention between Overflow and Counter Clearing
Rev. 2.00 Sep. 07, 2007 Page 565 of 1312
REJ09B0320-0200