SH7261 Datasheet, PDF (881/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.2 Transmit Cancel Register 0 (TXCR0)
TXCR0 is a 16-bit read/conditionally-write registers. The TXCR0 controls Mailbox-15 to
Mailbox-1.This register is used by the CPU to request the pending transmission requests in the
TXPR to be cancelled. To clear the corresponding bit in the TXPR the CPU must write a '1' to the
bit position in the TXCR. Writing a '0' has no effect.
When an abort has succeeded the CAN controller clears the corresponding TXPR + TXCR bits,
and sets the corresponding ABACK bit. However, once a Mailbox has started a transmission, it
cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding TXACK bit,
however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding ABACK bit. If
an attempt is made by the CPU to clear a mailbox transmission that is not transmit-pending it has
no effect. In this case the CPU will be not able at all to set the TXCR flag.
• TXCR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXCR0[15:1]
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* —
Note: * Only writing a '1' to a Mailbox that is requested for transmission and is configured as
transmit.
Bit 15 to 1 — Requests the corresponding Mailbox, that is in the queue for transmission, to cancel
its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1]) respectively.
Bit[15:1]:TXCR0
0
1
Description
Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition] Completion of transmit message cancellation
(automatically cleared)
Transmission cancellation request made for corresponding mailbox
Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has
no effect and always read back as a '0'.
Rev. 2.00 Sep. 07, 2007 Page 849 of 1312
REJ09B0320-0200