SH7261 Datasheet, PDF(901/1348 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7261 Datasheet, PDF (901/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

19.7 Interrupt Sources

Table 19.10 lists the RCAN-ET interrupt sources. With the exception of the reset processing

interrupt (IRR0) by a power-on reset, these sources can be masked. Masking is implemented using

the mailbox interrupt mask register 0 (MBIMR0) and interrupt mask register (IMR). For details on

the interrupt vector of each interrupt source, see section 6, Interrupt Controller (INTC).

Table 19.10 RCAN-ET Interrupt Sources

Channel Interrupt

0

ERS_0

OVR_0

SLE_0

RM1_0*2

RM0_0*2

Description

Error Passive Mode (TEC â¥ 128 or REC â¥ 128)

Bus Off (TEC â¥ 256)/Bus Off recovery

Error warning (TEC â¥ 96)

Error warning (REC â¥ 96)

Message error detection

Reset/halt/CAN sleep transition

Overload frame transmission

Unread message overwrite (overrun)

Detection of CAN bus operation in CAN sleep

mode

Message transmission/transmission disabled

(slot empty)

Data frame reception/

Remote frame reception

Interrupt

Flag

IRR5

IRR6

IRR3

IRR4

IRR13*1

IRR0

IRR7

IRR9

IRR12

IRR8

IRR1*3

IRR2*3

DTC

Activation

Not

possible

Possible

Rev. 2.00 Sep. 07, 2007 Page 869 of 1312

REJ09B0320-0200

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