SH7261 Datasheet, PDF (309/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Single read
CKIO
SDRAM command
ACT DSL RD PRA DSL
Data bus
d
DRCD
(ACT-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
DPCG
(PRA-next)
ACT: Row and bank activation command
RD: Read command
DSL: Deselect command
PRA: Precharge-all command
Note: If the interval set in DRAS ends before RD, PRA is issued in the table
size after RD.
Figure 9.37 Single Read Timing Example 2
Single read
CKIO
SDRAM command
ACT DSL RD PRA DSL
Data bus
d
DRCD
(ACT-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
DPCG
(PRA-next)
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
Figure 9.38 Single Read Timing Example 3
Rev. 2.00 Sep. 07, 2007 Page 277 of 1312
REJ09B0320-0200