SH7261 Datasheet, PDF (171/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.4.5 PINT Interrupts
PINT interrupts are input from pins PINT7 to PINT0. As regard to the setting method of pins
PINT7 to PINT0, see section 25, Pin Function Controller (PFC). Input of the interrupt requests is
enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register
(PINTER). For the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected
individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control
register 2 (ICR2). A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0
interrupts by bits 15 to 12 in interrupt priority register 05 (IPR05).
When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is
sent to the INTC while the PINT7 to PINT0 pins are low. An interrupt request signal is stopped
being sent to the INTC when the PINT7 to PINT0 pins are driven high. The status of the interrupt
requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the
PINT interrupt request register (PIRR). The above description also applies to when using high-
level sensing, except for the polarity being reversed. The PINT interrupt exception handling sets
the I3 to I0 bits in SR to the priority level of the PINT interrupt.
When restoring from the service routine of PINT interrupt exception handling, execute the RTE
instruction after an interrupt request has been cleared in the PINT interrupt request register
(PIRR).
6.4.6 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• A/D converter (ADC)
• CD-ROM decoder (ROM-DEC)
• Multi-function timer pulse unit 2 (MTU2)
• Realtime clock (RTC)
• Watchdog timer (WDT)
• I²C bus interface 3 (IIC3)
• Direct memory access controller (DMAC)
• Serial communication interface with FIFO (SCIF)
• Controller area network (RCAN-ET)
• IEBus^TM controller (IEB)
• Serial sound interface (SSI)
• 8-bit timer (TMR)
Rev. 2.00 Sep. 07, 2007 Page 139 of 1312
REJ09B0320-0200