SH7261 Datasheet, PDF (615/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Normal Mode
Figure 12.137 shows an explanatory diagram of the case where an error occurs in PWM mode 2
and operation is restarted in normal mode after re-setting.
1
2
3
4
5
Power-on TMDR TIOR PFC TSTR
reset (PWM2) (1 init (MTU2) (1)
MTU2
0 out)
module output
6
Match
7
8
9
10
11
12
13
Error PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
TIOC*A
Not initialized (cycle register)
TIOC*B
Port output
PB, PC, PD*¹
High-Z
PB, PC, PD*²
High-Z
Notes: 1. This pin is multiplexed with TIOC*A.
2. This pin is multiplexed with TIOC*B.
Figure 12.137 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
1. After a reset, MTU2 output is low and ports are in the high-impedance state.
2. Set PWM mode 2.
3. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the
example, TIOC *A is the cycle register.)
4. Set MTU2 output with the PFC.
5. The count operation is started by TSTR.
6. Output goes low on compare-match occurrence.
7. An error occurs.
8. Set port output with the PFC and output the inverse of the active level.
9. The count operation is stopped by TSTR.
10. Set normal mode.
11. Initialize the pins with TIOR.
12. Set MTU2 output with the PFC.
13. Operation is restarted by TSTR.
Rev. 2.00 Sep. 07, 2007 Page 583 of 1312
REJ09B0320-0200