SH7261 Datasheet, PDF (915/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
The master unit enters the subsequent message length field output state after confirming the
acknowledgement.
When the acknowledgement is not confirmed, the master unit enters the waiting (monitor) state,
and communications ends. However, in the case of broadcast communications, the master unit
enters the following message length field output state without confirming the acknowledgement.
For details of the contents of the control bit, see table 20.4.
(5) Message Length Field
The message length field is a field for specifying the number of transfer bytes. The message length
field is comprised of message length bits, a parity bit, and an acknowledge bit.
The message length has eight bits and the MSB is output first. Table 20.3 shows the number of
transfer bytes.
Table 20.3 Contents of Message Length bits
Message Length bits (Hexadecimal)
Number of Transfer Bytes
H'01
1 byte
H'02
2 bytes
:
:
H'FF
255 bytes
H'00
256 bytes
Note:
If a number greater than the maximum number of transfer bytes in one frame is specified,
communications are done in multiple frames depending on the communications mode. In
this case, the message length bits indicate the number of remaining communications data
after the first transfer. In this LSI, the message length bits must be smaller than the
maximum number of transfer bytes in one frame. Set these within the ranges shown below.
Mode 0: 1 to 16 bytes
Mode 1: 1 to 32 bytes
Mode 2: 1 to 128 bytes
This field operation differs depending on the value of bit 3 in the control field: master
transmission (the bit 3 of the control bits is 1) or master reception (the bit 3 of the control bits is
0).
Rev. 2.00 Sep. 07, 2007 Page 883 of 1312
REJ09B0320-0200