SH7261 Datasheet, PDF (1038/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.5 Interrupt Sources
21.5.1 Interrupt and DMA Transfer Request Signals
Table 21.3 lists the interrupt signals and DMA transfer request signal generated by the CD-ROM
decoder, along with the meanings and the modules to which the signals are connected.
Table 21.3 Interrupt and DMA Transfer Request Signals
Name
ISEC
ITARG
ISY
IERR
IBUF
IREADY
DMA transfer
request
Description
Connected To
Transitions from sector to sector
INTC
Access to a CD-ROM sector that is not the expected target
sector
INTC
A sync code from the CD-ROM with abnormal timing
INTC
An error that was not correctable by ECC correction or an error INTC
indicated by EDC checking after ECC correction
State changes in data transfer to the buffer
INTC
Request for data transfer to the buffer for CD-ROM
INTC
Request for data transfer to the buffer for CD-ROM
DMAC
The above interrupt signals are generated by the following sources
(1) ISEC
This interrupt is generated when the sync code indicates a transition from sector to sector.
(2) ITARG
This interrupt reports that the stream data transferred from the CD-DSP is not the data of the target
sector. The CD-ROM decoder checks the time data in the subcode. In correct operation, data
transfer is expected to start slightly before the target sector. An ITARG interrupt is generated in
the following cases.
• When data of a sector preceding the target sector by quite a few sectors have been transferred
• When data of a sector that comes after the target sector have been transferred
For the generation of this interrupt, ITARG is detected from the subcode. However, this interrupt
has no meaning in this LSI because CD-ROM data are transferred from the SSI module.
Rev. 2.00 Sep. 07, 2007 Page 1006 of 1312
REJ09B0320-0200