SH7261 Datasheet, PDF (686/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Realtime Clock (RTC)
15.3.13 Date Alarm Register (RDAYAR)
RDAYAR is an alarm register corresponding to the BCD coded date counter RDAYCNT. When
the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
The assignable range is from 01 through 31 + ENB bits (practically in BCD), otherwise operation
errors occur.
The ENB bit in RDAYAR is initialized by a power-on reset or in deep standby mode. The other
bits are not initialized by a power-on reset or manual reset, or in deep standby and software
standby modes.
Bit: 7
6
5
4
3
2
1
0
ENB — 10 days
1 day
Initial value: 0
0 ——————
R/W: R/W R R/W R/W R/W R/W R/W R/W
Bit Bit Name
7
ENB
6

5, 4 10 days
3 to 0 1 day
Initial
Value
R/W
0
R/W
0
R
Undefined R/W
Undefined R/W
Description
When this bit is set to 1, a comparison with the
RDAYCNT value is performed.
Reserved
This bit is always read as 0. The write value should
always be 0.
Ten's position of dates setting value
One's position of dates setting value
Rev. 2.00 Sep. 07, 2007 Page 654 of 1312
REJ09B0320-0200