SH7261 Datasheet, PDF (295/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(b) Single Read/Single Write Access
Figure 9.19 shows a timing example for single read operation and figure 9.20 for single write
operation. The access timing is modified by means of settings in the SDRAMm timing register
(SDmTR).
Single read
CKIO
SDRAM command
ACT RD PRA
Data bus
d0
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
Figure 9.19 Single Read Timing Example (Shortest Timing Settings)
Single write
CKIO
SDRAM command
ACT WR PRA
Data bus
d0
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
Figure 9.20 Single Write Timing Example (Shortest Timing Settings)
Rev. 2.00 Sep. 07, 2007 Page 263 of 1312
REJ09B0320-0200