SH7261 Datasheet, PDF (986/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Table 21.2 Register Settings for Sync Code Maintenance Modes
SY_AUT
1
0
0
0
0
SY_IEN

0
1
1
0
SY_DEN

1
0
1
0
Operating Mode
Automatic sync maintenance mode
External sync mode
Interpolated sync mode
Interpolated sync plus external sync mode
Setting prohibited
21.3.3 Decoding Mode Control Register (CROMCTL0)
CROMCTL0 enables/disables the various functions, selects criteria for mode or form
determination, and specifies the sector type. The setting of this register becomes valid at the
sector-to-sector transition
Bit: 7
MD_
DESC
Initial value: 1
R/W: R/W
6
—
0
R/W
5
4
3
2
1
0
MD_ MD_ MD_
AUTO AUTOS1 AUTOS2
MD_SEC[2:0]
0
0
0
0
1
0
R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value
7
MD_DESC 1
6

0
5
MD_AUTO 0
R/W Description
R/W Descrambling Function ON/OFF
0: Descrambling function is off
1: Descrambling function is on
R/W Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Automatic Mode/Form Detection ON/OFF
0: Off
1: On
Detectable formats are Mode 0, Mode 1, Mode 2 (non-
XA), Mode 2 Form 1, and Mode 2 Form 2. If the mode
and form cannot be detected, the sector is taken to be
in the same mode and form as the previous sector. If
the mode and form of the first sector after decoding
starts is undetectable, the setting of the MD_SEC[2:0]
bits is used as the initial value.
Rev. 2.00 Sep. 07, 2007 Page 954 of 1312
REJ09B0320-0200