SH7261 Datasheet, PDF (330/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
10.1.4 Bus Error Control Register (SYCBESW)
SYCBESW controls the notification of various types of bus errors to the CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
00
01
CPEN CPEN
—
11
CPEN
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R/W R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value
31
00CPEN 0
30
01CPEN 0
29

0
28
11CPEN 0
27 to 0 
All 0
R/W Description
R/W Bus Error Control (CPU → CPU)
This bit controls notification to the CPU when a bus
error is caused by the CPU.
0: Not notified
1: Notified
R/W Bus Error Control (DMAC Destination Side → CPU)
This bit controls notification to the CPU when a bus
error is caused by the DMAC destination side.
0: Not notified
1: Notified
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Bus Error Control (DMAC Source Side → CPU)
This bit controls notification to the CPU when a bus
error is caused by the DMAC source side.
0: Not notified
1: Notified
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 298 of 1312
REJ09B0320-0200