SH7261 Datasheet, PDF (246/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
21, 20 BSIZE[1:0] 00*¹
R/W External Bus Width Select
These bits specify the width of the data bus for the
external device of the corresponding channel of CSC.
The initial value for the data bus width for CSC channel
0 (CS0) differs depending on the settings of pins MD1
and MD0.
10: 8-bit bus
00: 16-bit bus
01: 32-bit bus
19 to 17 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
16
EXENB
0*²
R/W Operation Enable
This bit enables or disables the operation for the
corresponding channel of CSC. The initial value
corresponding to CS0 only is operation enabled
(EXENB = 1).
0: Operation disabled
1: Operation enabled
15 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. The initial value of the BSIZE bits in CS0 differs depending on the settings of pins MD1
and MD0.
2. The initial value of the EXENB bit in CS0 is 1.
To disable the operation for each channel, forcibly write out data tentatively stored in internal
write buffer. The procedure is as follows:
1. Execute read access to the channel whose operation is to be disabled.
2. Then, write 0 to the EXENB bit (operation disabled).
Rev. 2.00 Sep. 07, 2007 Page 214 of 1312
REJ09B0320-0200