SH7261 Datasheet, PDF (95/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.4.10 Bit Manipulation Instructions
Table 2.19 Bit Manipulation Instructions
Instruction
BAND.B
#imm3,@(disp12,Rn)
BANDNOT.B #imm3,@(disp12,Rn)
BCLR.B
#imm3,@(disp12,Rn)
BCLR
BLD.B
#imm3,Rn
#imm3,@(disp12,Rn)
BLD
#imm3,Rn
BLDNOT.B #imm3,@(disp12,Rn)
BOR.B
#imm3,@(disp12,Rn)
BORNOT.B #imm3,@(disp12,Rn)
BSET.B
#imm3,@(disp12,Rn)
BSET
BST.B
#imm3,Rn
#imm3,@(disp12,Rn)
BST
BXOR.B
#imm3,Rn
#imm3,@(disp12,Rn)
Instruction Code
0011nnnn0iii1001
0100dddddddddddd
0011nnnn0iii1001
1100dddddddddddd
0011nnnn0iii1001
0000dddddddddddd
10000110nnnn0iii
0011nnnn0iii1001
0011dddddddddddd
10000111nnnn1iii
0011nnnn0iii1001
1011dddddddddddd
0011nnnn0iii1001
0101dddddddddddd
0011nnnn0iii1001
1101dddddddddddd
0011nnnn0iii1001
0001dddddddddddd
10000110nnnn1iii
0011nnnn0iii1001
0010dddddddddddd
10000111nnnn0iii
0011nnnn0iii1001
0110dddddddddddd
Operation
(imm of (disp + Rn)) & T → T
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
3
Operation
Yes
result
~(imm of (disp + Rn)) & T → T 3
Ope-ration
Yes
result
0 → (imm of (disp + Rn))
3

Yes
0 → imm of Rn
1

Yes
(imm of (disp + Rn)) → T
3
Operation
Yes
result
imm of Rn → T
1
Operation
Yes
result
~(imm of (disp + Rn))
3
Operation
Yes
→T
result
( imm of (disp + Rn)) | T → T 3
Operation
Yes
result
~( imm of (disp + Rn)) | T → T 3
Operation
Yes
result
1 → ( imm of (disp + Rn))
3

Yes
1 → imm of Rn
1

Yes
T → (imm of (disp + Rn))
3

Yes
T → imm of Rn
1

Yes
(imm of (disp + Rn)) ^ T → T 3
Operation
Yes
result
Rev. 2.00 Sep. 07, 2007 Page 63 of 1312
REJ09B0320-0200