SH7261 Datasheet, PDF (829/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

7. Parallel Right-Aligned with Delay
As basic sample format configuration except PDTA = 1
SSISCK
Section 18 Serial Sound Interface (SSI)
SSIWS
1st Channel
2nd Channel
SSIDATA TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3
8. Mute Enabled
Figure 18.17 Parallel Right-Aligned with Delay
As basic sample format configuration except MUEN = 1 (TD data ignored)
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18.18 Mute Enabled
Rev. 2.00 Sep. 07, 2007 Page 797 of 1312
REJ09B0320-0200