SH7261 Datasheet, PDF (243/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4 Register Descriptions
The BSC has the following registers.
All registers are initialized by a power-on reset or in deep standby mode.
Do not access spaces other than area 0 until settings are completed for the connected memory
interface.
Table 9.4 Register Configuration
Register Name
CS0 control register
Abbreviation R/W
CS0CNT
R/W
CS0 recovery cycle setting
CS0REC
R/W
register
CS1 control register
CS1CNT
R/W
CS1 recovery cycle setting
CS1REC
R/W
register
CS2 control register
CS2CNT
R/W
CS2 recovery cycle setting
CS2REC
R/W
register
CS3 control register
CS3CNT
R/W
CS3 recovery cycle setting
CS3REC
R/W
register
CS4 control register
CS4CNT
R/W
CS4 recovery cycle setting
CS4REC
R/W
register
CS5 control register
CS5CNT
R/W
CS5 recovery cycle setting
CS5REC
R/W
register
CS6 control register
CS6CNT
R/W
CS6 recovery cycle setting
CS6REC
R/W
register
Initial Value Address
Access
Size
H'00010000/ H'FF420000 8, 16, 32
H'00110000/
H'00210000*
H'00000000 H'FF420008 8, 16, 32
H'00000000 H'FF420010 8, 16, 32
H'00000000 H'FF420018 8, 16, 32
H'00000000 H'FF420020 8, 16, 32
H'00000000 H'FF420028 8, 16, 32
H'00000000 H'FF420030 8, 16, 32
H'00000000 H'FF420038 8, 16, 32
H'00000000 H'FF420040 8, 16, 32
H'00000000 H'FF420048 8, 16, 32
H'00000000 H'FF420050 8, 16, 32
H'00000000 H'FF420058 8, 16, 32
H'00000000 H'FF420060 8, 16, 32
H'00000000 H'FF420068 8, 16, 32
Rev. 2.00 Sep. 07, 2007 Page 211 of 1312
REJ09B0320-0200