SH7261 Datasheet, PDF (304/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(d) Timing Register Set Values and Access Timing
The correspondence between the SDRAMm timing register (SDmTR) set values and the read and
write access timing is described below.
• Multiple Read Timing Setting Examples
Figures 9.30 to 9.32 show the correspondence between the timing of multiple read operations
involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table
9.12 shows the SDRAMm timing register (SDmTR) set values for each figure.
Table 9.12 SDITR Set Value Correspondence Table (Multiple Read Timing)
Figure
Figure 9.30
Figure 9.31
Figure 9.32
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DCL
010
010
011
Multiple read
CKIO
SDRAM command
ACT RD
RD
RD
RD PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
DPCG
(PRA-next)
Figure 9.30 Multiple Read Timing Example 1
Rev. 2.00 Sep. 07, 2007 Page 272 of 1312
REJ09B0320-0200