SH7261 Datasheet, PDF (1338/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

CPU .......................................................... 23
Crystal oscillator....................................... 79
CSC interface.......................................... 242
D
D/A converter (DAC) ........................... 1037
D/A converter characteristics ............... 1291
D/A output hold function in software
standby mode........................................ 1042
Data array ....................................... 188, 201
Data array read ....................................... 202
Data array write ...................................... 202
Data format in registers ............................ 28
Data formats in memory ........................... 28
Data transfer instructions.......................... 48
DC characteristics................................. 1250
Dead time compensation ........................ 534
Definitions of A/D conversion
accuracy................................................ 1031
Delayed branch instructions ..................... 31
Denormalized numbers............................. 70
Direct memory access controller
(DMAC) ................................................. 305
Displacement accessing............................ 33
Divider...................................................... 79
E
Effective address calculation .................... 34
Equation for getting SCBRR value......... 692
Exception handling ................................... 95
Exception handling state........................... 65
Exception handling vector table ............... 99
Exception source generation immediately
after delayed branch instruction.............. 114
Exceptions triggered by instructions ...... 111
External pulse width measurement......... 533
External trigger input timing ................ 1030
Rev. 2.00 Sep. 07, 2007 Page 1306 of 1312
REJ09B0320-0200
F
Floating point operation instructions ........ 60
Floating-point ranges ................................ 69
Floating-point registers ............................. 71
Floating-point unit (FPU) ......................... 67
Format of double-precision
floating-point number ............................... 68
Format of single-precision
floating-point number ............................... 67
FPU exception........................................... 75
FPU-related CPU instructions................... 62
Full-scale error...................................... 1032
G
General illegal instructions ..................... 112
General registers ....................................... 23
Global base register (GBR)....................... 26
H
Halt mode................................................ 858
H-UDI commands................................. 1156
H-UDI interrupt ............................ 137, 1159
H-UDI reset .......................................... 1159
H-UDI-related pin timing ..................... 1286
I
I/O port timing ...................................... 1285
I/O ports ................................................ 1043
I²C bus format......................................... 748
I²C bus interface 3 (IIC3)........................ 729
ID Reorder .............................................. 824
IEBus controller (IEB) ........................ 875
IIC3 module timing............................... 1281
Immediate data.......................................... 32
Immediate data accessing ......................... 32
Immediate data format .............................. 29
Initial values of general registers .............. 27