SH7261 Datasheet, PDF (68/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Addressing Mode Instruction Format Effective Address Calculation
Equation
Indexed GBR
indirect
@(R0,GBR)
The effective address is the sum of GBR value GBR + R0
and R0.
GBR
+
GBR + R0
TBR duplicate
indirect with
displacement
PC indirect with
displacement
R0
@@ (disp:8,TBR) The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
TBR
Contents of
address (TBR +
disp × 4)
disp
+
(zero-extended)
×
4
TBR
+ disp × 4
(TBR
+ disp × 4)
@(disp:8,PC)
The effective address is the sum of PC value Word:
and an 8-bit displacement (disp). The value of PC + disp × 2
disp is zero-extended, and is doubled for a word _Longword:
operation, and quadrupled for a longword
PC &
operation. For a longword operation, the lowest _{H'FFFFFFFC +}
two bits of the PC value are masked.
disp × 4
PC
(for longword)
&
H'FFFFFFFC
+
disp
(zero-extended)
×
PC + disp × 2
or
PC & H'FFFFFFFC
+ disp × 4
PC relative
disp:8
2/4
The effective address is the sum of PC value
and the value that is obtained by doubling the
sign-extended 8-bit displacement (disp).
PC
disp
+
(sign-extended)
×
PC + disp × 2
PC + disp × 2
2
Rev. 2.00 Sep. 07, 2007 Page 36 of 1312
REJ09B0320-0200