SH7261 Datasheet, PDF (163/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.8 Bank Control Register (IBCR)
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority
level. IBCR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Bit Name Value R/W Description
15
E15
0
R/W Enable
14
E14
13
E13
12
E12
11
E11
10
E10
0
R/W These bits enable or disable use of register banks for
0
R/W ^{interrupt priority levels 15 to 1. However, use of register}
banks is always disabled for the user break interrupts.
0
R/W _{0: Use of register banks is disabled}
0
R/W _{1: Use of register banks is enabled}
0
R/W
9
E9
0
R/W
8
E8
0
R/W
7
E7
0
R/W
6
E6
0
R/W
5
E5
0
R/W
4
E4
0
R/W
3
E3
0
R/W
2
E2
0
R/W
1
E1
0
R/W
0

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 131 of 1312
REJ09B0320-0200