SH7261 Datasheet, PDF (893/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
The following table shows conditions to access registers.
Table 19.8 Conditions to Access Registers
MCR IRR
Status Mode GSR IMR
BCR
Reset
Yes
Yes
Yes
Transmission Yes
Yes
No*¹
Reception
Halt Request Yes
Yes
No*¹
Halt
Yes
Yes
No*¹
Sleep
Yes
Yes
No
Notes: 1. No hardware protection
2. When TXPR is not set.
RCAN-ET Registers
mailbox
mailbox mailbox
MBIMR Flag_register (ctrl0, LAFM) (data) (ctrl1)
Yes
Yes
Yes
Yes
Yes
No*¹
Yes
Yes*² Yes*²
Yes
No*¹ Yes*²
Yes
Yes
Yes
Yes
No
No
No*¹ Yes*² Yes*²
Yes
Yes
No
No
No*¹ Yes*²
Yes
No
19.6.2 Test Mode Settings
The RCAN-ET has various test modes. The register TST[2:0] (MCR[10:8]) is used to select the
RCAN-ET test mode. The default (initialized) settings allow RCAN-ET to operate in Normal
mode. The following table is examples for test modes.
Test Mode can be selected only while in configuration mode. The user must then exit the
configuration mode (ensuring BCR0/BCR1 is set) in order to run the selected test mode.
Table 19.9 Test Mode Settings
Bit10:
TST2
0
0
0
0
1
1
1
1
Bit9:
TST1
0
0
1
1
0
0
1
1
Bit8:
TST0
0
1
0
1
0
1
0
1
Description
Normal mode (initial value)
Listen-only mode (receive-only mode)
Self test mode 1 (external)
Self test mode 2 (internal)
Write error counter
Error passive mode
Setting prohibited
Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 861 of 1312
REJ09B0320-0200