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SH7261 Datasheet, PDF (83/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Instruction
NOTT
PREF @Rn
SWAP.B Rm,Rn
SWAP.W Rm,Rn
XTRCT Rm,Rn
Section 2 CPU
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
0000000001101000 ~T â T
1
Ope-
Yes
ration
result
0000nnnn10000011 (Rn) â operand cache
1

Yes Yes
0110nnnnmmmm1000 Rm â swap lower 2 bytes â 1
Rn
 Yes Yes Yes
0110nnnnmmmm1001 Rm â swap upper and lower 1
words â Rn
 Yes Yes Yes
0010nnnnmmmm1101 Middle 32 bits of Rm:Rn â Rn 1
 Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 51 of 1312
REJ09B0320-0200
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