SH7261 Datasheet, PDF (506/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) Example of Cascaded Operation Setting Procedure
Figure 12.20 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
Start count
[1] Set bits TPSC2 to TPSC0 in the channel 1
[1]
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
[2]
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
<Cascaded operation>
Figure 12.20 Cascaded Operation Setting Procedure
(2) Cascaded Operation Example (a)
Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
0000
0001
0000
Figure 12.21 Cascaded Operation Example (a)
Rev. 2.00 Sep. 07, 2007 Page 474 of 1312
REJ09B0320-0200