SH7261 Datasheet, PDF (582/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3) TCFV Flag/TCFU Flag Setting Timing
Figure 12.103 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV
interrupt request signal timing.
Figure 12.104 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 12.103 TCIV Interrupt Setting Timing
Pφ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 12.104 TCIU Interrupt Setting Timing
Rev. 2.00 Sep. 07, 2007 Page 550 of 1312
REJ09B0320-0200