SH7261 Datasheet, PDF (306/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
• Multiple Write Timing Setting Examples
Figures 9.33 to 9.35 show the correspondence between the timing of multiple write operations
involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table
9.13 shows the SDRAMm timing register (SDmTR) set values for each figure.
Table 9.13 SDITR Set Value Correspondence Table (Multiple Write Timing)
Figure
Figure 9.33
Figure 9.34
Figure 9.35
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DWR
0
0
1
Multiple write
CKIO
SDRAM command
ACT WR WR WR WR PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-WR)
DWR
DPCG
(WR-PRA) (PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
Figure 9.33 Multiple Write Timing Example 1
Rev. 2.00 Sep. 07, 2007 Page 274 of 1312
REJ09B0320-0200