SH7261 Datasheet, PDF (641/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
TCR
TCCR
Channel
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
All
1
0
1

Uses external clock. Counts at rising edge*².
1
1
0

Uses external clock. Counts at falling edge*².
1
1
1

Uses external clock. Counts at both rising and falling
edges*².
Notes: 1. If the clock input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. To use the external clock, the function of the corresponding pin should be selected
using the pin function controller (PFC). For details, see section 25, Pin Function
Controller (PFC).
13.3.6 Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
• TCSR_0
• TCSR_1
Bit: 7
6
5
4
3
2
CMFB CMFA OVF ADTE OS[3:2]
10
OS[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W:R/(W)*R/(W)*R/(W)* R/W R/W R/W R/W R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit: 7
6
5
4
3
2
1
0
CMFB CMFA OVF — OS[3:2]
OS[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W:R/(W)*R/(W)*R/(W)* R R/W R/W R/W R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Rev. 2.00 Sep. 07, 2007 Page 609 of 1312
REJ09B0320-0200