SH7261 Datasheet, PDF (222/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 Cache
8.2 Register Descriptions
The cache has the following registers.
Table 8.2 Register Configuration
Register Name
Cache control register 1
Cache control register 2
Abbreviation R/W
CCR1
R/W
CCR2
R/W
Initial Value
H'00000000
H'00000000
Address
Access Size
H'FFFC1000 32
H'FFFC1004 32
8.2.1 Cache Control Register 1 (CCR1)
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or
write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in an address space that is not
cached, and an address space that is cached should be accessed after reading the contents of
CCR1.
CCR1 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a
manual reset or in software standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
    ICF   ICE     OCF  WT OCE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R R R/W R R R R R/W R R/W R/W
Rev. 2.00 Sep. 07, 2007 Page 190 of 1312
REJ09B0320-0200