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| SH7261 Datasheet, PDF (1294/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 31 Electrical Characteristics
31.3.2 Control Signal Timing
Table 31.6 Control Signal Timing
Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V,
PVCC â 0.3 V ⤠AVCC ⤠PVCC, AVref = 3.0 V to AVCC,
PVSS = VSSR = PLLVSS = AVSS = 0 V
BÏ = 60 MHz
Item
Symbol Min.
Max.
Unit Figure
RES pulse width
RES setup time*1
MRES pulse width
MRES setup time*1
NMI pulse width
NMI setup time*1
tRESW
20*2

tRESS
200

t
MRESW
20*3

t
MRESS
200

t
NMIW
20*4

t
NMIS
150

tcyc
Figures 31.4, 31.5,
ns and 31.8
t
cyc
ns
t
Figures 31.6 and
cyc
ns 31.9
NMI hold time
IRQ7 to IRQ0 pulse width
IRQ7 to IRQ0 setup time*1
tNMIH
10

ns
t
IRQW
20*4

t
cyc
tIRQS
150

ns
IRQ7 to IRQ0 hold time
tIRQH
10

ns
PINT7 to PINT0 setup time*1
tPINTS
150

ns
Notes: 1. The RES, MRES, NMI, IRQ7 to IRQ0 and PINT7 to PINT0 signals are asynchronous
signals. When the setup time is satisfied, change of signal level is detected at the rising
edge of the clock. If not, the detection can be delayed until the rising edge of the next
clock.
2. In software standby mode, deep standby mode or when the clock multiplication ratio is
changed, tRESW = tOSC2 (min).
3. In software standby mode or deep standby mode, tMRESW = tOSC2 (min).
4. In software standby mode or deep standby mode, t /t NMIW IRQW = tOSC3 (min).
Rev. 2.00 Sep. 07, 2007 Page 1262 of 1312
REJ09B0320-0200
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