SH7261 Datasheet, PDF (220/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 Cache
Address array (ways 0 to 3)
Data array (ways 0 to 3)
Entry 0 V U Tag address
Entry 1
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0 _LW0
1
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LW1
LW2
LW3
LRU
0
1
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Entry 127
23 (1 + 1 + 21) bits
127
128 (32 × 4) bits
LW0 to LW3: Longword data 0 to 3
127
6 bits
Figure 8.1 Operand Cache Structure
(1) Address Array
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid.
The U bit (only for operand cache) indicates whether the entry has been written to in write-back
mode. When the U bit is 1, the entry has been written to; when 0, it has not.
The tag address holds the physical address used in the external memory access. It is composed of
21 bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, as values of
addresses in the cache valid space are from H'00000000 to H'1FFFFFFF (see section 9, Bus State
Controller (BSC)), the upper three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset and in deep standby mode but not
initialized by a manual reset or in software standby mode.
The tag address is not initialized by a power-on reset or manual reset or in software standby mode.
The tag address becomes undefined after deep standby.
(2) Data Array
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes).
The data array is not initialized by a power-on reset or manual reset or in software standby mode.
The data array becomes undefined after deep standby.
Rev. 2.00 Sep. 07, 2007 Page 188 of 1312
REJ09B0320-0200