SH7261 Datasheet, PDF (1307/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
31.3.4 DMAC Module Timing
Table 31.8 DMAC Module Timing
Conditions:
PV_CC = V_CCR = PLLV_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V,
PV_CC − 0.3 V ≤ AV_CC ≤ PV_CC, AV_ref = 3.0 V to AV_CC,
PV_SS = V_SSR = PLLV_SS = AV_SS = 0 V
Item
DREQ setup time
DREQ hold time
DACK, DACT, DTEND delay time
Symbol Min.
t_DRQS
15
t
15
DRQH
t
DACD

Max. Unit

ns

15
Figure
Figure 31.22
Figure 31.23
CKIO
DREQn
t_DRQS t_DRQH
Note: n = 0 to 3
Figure 31.22 DREQ Input Timing
CKIO
DACKn
DACTn
DTENDn
t
DACD
Note: n = 0 to 3
t
DACD
Figure 31.23 DACK, DACT, DTEND Output Timing
Rev. 2.00 Sep. 07, 2007 Page 1275 of 1312
REJ09B0320-0200