SH7261 Datasheet, PDF (115/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Clock
Operating FRQCR
Mode
Setting
PLL Frequency
Multiplier
Ratio of
Internal Clock
Selectable Frequency Range (MHz)
PLL
PLL
Frequencies
Output Clock Internal Clock Bus Clock
Circuit 1 Circuit 2 (I:B:P)*¹
Input Clock*² (CKIO Pin)*³ (Iφ)*³
(Bφ)*³
0
H'1313 ON (×4) ON (×4) 8:4:4
10
40
80
40
H'1315 ON (×4) ON (×4) 8:4:2
10 to 12.5
40 to 50
80 to 100
40 to 50
H'1316 ON (×4) ON (×4) 8:4:4/3
10 to 12.5
40 to 50
80 to 100
40 to 50
H'1333 ON (×4) ON (×4) 4:4:4
10
40
40
40
H'1335 ON (×4) ON (×4) 4:4:2
10 to 12.5
40 to 50
40 to 50
40 to 50
H'1336 ON (×4) ON (×4) 4:4:4/3
10 to 12.5
40 to 50
40 to 50
40 to 50
2
H'1000 ON (×1) ON (×2) 2:2:2
10 to 20
20 to 40
20 to 40
20 to 40
H'1001 ON (×1) ON (×2) 2:2:1
10 to 30
20 to 60
20 to 60
20 to 60
H'1002 ON (×1) ON (×2) 2:2:2/3
10 to 30
20 to 60
20 to 60
20 to 60
H'1003 ON (×1) ON (×2) 2:2:1/2
10 to 30
20 to 60
20 to 60
20 to 60
H'1004 ON (×1) ON (×2) 2:2:1/3
10 to 30
20 to 60
20 to 60
20 to 60
H'1005 ON (×1) ON (×2) 2:2:1/4
10 to 30
20 to 60
20 to 60
20 to 60
H'1006 ON (×1) ON (×2) 2:2:1/6
10 to 30
20 to 60
20 to 60
20 to 60
H'1101 ON (×2) ON (×2) 4:2:2
10 to 20
20 to 40
40 to 80
20 to 40
H'1103 ON (×2) ON (×2) 4:2:1
10 to 30
20 to 60
40 to 120
20 to 60
H'1104 ON (×2) ON (×2) 4:2:2/3
10 to 30
20 to 60
40 to 120
20 to 60
H'1105 ON (×2) ON (×2) 4:2:1/2
10 to 30
20 to 60
40 to 120
20 to 60
H'1106 ON (×2) ON (×2) 4:2:1/3
10 to 30
20 to 60
40 to 120
20 to 60
H'1111 ON (×2) ON (×2) 2:2:2
10 to 20
20 to 40
20 to 40
20 to 40
H'1113 ON (×2) ON (×2) 2:2:1
10 to 30
20 to 60
20 to 60
20 to 60
H'1114 ON (×2) ON (×2) 2:2:2/3
10 to 30
20 to 60
20 to 60
20 to 60
H'1115 ON (×2) ON (×2) 2:2:1/2
10 to 30
20 to 60
20 to 60
20 to 60
H'1116 ON (×2) ON (×2) 2:2:1/3
10 to 30
20 to 60
20 to 60
20 to 60
H'1202 ON (×3) ON (×2) 6:2:2
10 to 20
20 to 40
60 to 120
20 to 40
H'120C ON (×3) ON (×2) 6:2:1
20
40
120
40
H'120E ON (×3) ON (×2) 6:2:1/2
20
40
120
40
H'1206 ON (×3) ON (×2) 6:2:1/2
10 to 20
20 to 40
60 to 120
20 to 40
H'1222 ON (×3) ON (×2) 2:2:2
10 to 20
20 to 40
20 to 40
20 to 40
H'1224 ON (×3) ON (×2) 2:2:1
10 to 20
20 to 40
20 to 40
20 to 40
H'122C ON (×3) ON (×2) 2:2:1
20 to 30
40 to 60
40 to 60
40 to 60
Peripheral
Clock (Pφ)*³
40
20 to 25
13.33 to 16.67
40
20 to 25
13.33 to 16.67
20 to 40
10 to 30
6.67 to 20
5 to 15
3.33 to 10
2.5 to 7.5
1.67 to 5
20 to 40
10 to 30
6.67 to 20
5 to 15
3.3 to 10
20 to 40
10 to 30
6.67 to 20
5 to 15
3.3 to 10
20 to 40
20
10
5 to 10
20 to 40
10 to 20
20 to 30
Rev. 2.00 Sep. 07, 2007 Page 83 of 1312
REJ09B0320-0200