SH7261 Datasheet, PDF (1312/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
31.3.9 SCIF Module Timing
Table 31.13 SCIF Module Timing
Conditions: PV_CC = V_CCR = PLLV_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V,
PV_CC − 0.3 V ≤ AV_CC ≤ PV_CC, AV_ref = 3.0 V to AV_CC,
PV_SS = V_SSR = PLLV_SS = AV_SS = 0 V
Item
Symbol Min.
Max.
Unit
Input clock cycle (Clocked synchronous) t_Scyc
12
(Asynchronous)
4
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(Clocked synchronous)
t
SCKr
t
SCKf
t
SCKW
t_TXD
—
—
0.4
—

t_pcyc

t
pcyc
1.5
t
pcyc
1.5
t
pcyc
0.6
t
Scyc
3 t_pcyc + 15 ns
Receive data setup time
(Clocked synchronous)
t_RXS
4 t_pcyc + 15 
ns
Receive data hold time
(Clocked synchronous)
t_RXH
1 t_pcyc + 15 
ns
Note:
t
pcyc
indicates
a
peripheral
clock
(Pφ)
cycle.
Figure
Figure 31.31
Figure 31.32
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 31.31 SCK Input Clock Timing
SCK
TxD
(data transmit)
RxD
(data receive)
t_Scyc
t_TXD
t_RXS t_RXH
Figure 31.32 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 2.00 Sep. 07, 2007 Page 1280 of 1312
REJ09B0320-0200