SH7261 Datasheet, PDF (227/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 Cache
Table 8.6 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1)
LRU (Bits 5 to 0)
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
2
1
0
Table 8.7 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
LRU (Bits 5 to 0)
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
Way to be Replaced
1
0
8.3 Operation
Operations for the operand cache are described here. Operations for the instruction cache are
similar to those for the operand cache except for the address array not having the U bit, and there
being no prefetch operation or write operation, or a write-back buffer.
8.3.1 Searching Cache
If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is
accessed, the cache will be searched to see if the desired data is in the cache. Figure 8.2 illustrates
the method by which the cache is searched.
Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of
that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits
31 to 11 of the address used to access memory are compared with the read tag address. The
address comparison uses all four ways. When the comparison shows a match and the selected
entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the
selected entry is not valid (V = 0), a cache miss occurs. Figure 8.2 shows a hit on way 1.
Rev. 2.00 Sep. 07, 2007 Page 195 of 1312
REJ09B0320-0200