SH7261 Datasheet, PDF (11/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

5.2.2 Types of Reset ...................................................................................................... 101
5.2.3 Power-On Reset .................................................................................................... 102
5.2.4 Manual Reset ........................................................................................................ 104
5.3 Address Errors ................................................................................................................... 105
5.3.1 Address Error Sources .......................................................................................... 105
5.3.2 Address Error Exception Handling ....................................................................... 106
5.4 Bus Error............................................................................................................................ 106
5.4.1 Bus Error Generation Source ................................................................................ 106
5.4.2 Bus Error Exception Handling.............................................................................. 106
5.5 Register Bank Errors.......................................................................................................... 107
5.5.1 Register Bank Error Sources................................................................................. 107
5.5.2 Register Bank Error Exception Handling ............................................................. 107
5.6 Interrupts............................................................................................................................ 108
5.6.1 Interrupt Sources................................................................................................... 108
5.6.2 Interrupt Priority Level ......................................................................................... 109
5.6.3 Interrupt Exception Handling ............................................................................... 110
5.7 Exceptions Triggered by Instructions ................................................................................ 111
5.7.1 Types of Exceptions Triggered by Instructions .................................................... 111
5.7.2 Trap Instructions ................................................................................................... 112
5.7.3 Slot Illegal Instructions ......................................................................................... 112
5.7.4 General Illegal Instructions................................................................................... 112
5.7.5 Integer Division Instructions................................................................................. 113
5.7.6 Floating-point Operation Instruction .................................................................... 113
5.8 When Exception Sources Are Not Accepted ..................................................................... 114
5.9 Stack Status after Exception Handling Ends...................................................................... 115
5.10 Usage Notes ....................................................................................................................... 117
5.10.1 Value of Stack Pointer (SP) .................................................................................. 117
5.10.2 Value of Vector Base Register (VBR) .................................................................. 117
5.10.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 117
Section 6 Interrupt Controller (INTC) ...............................................................119
6.1 Features.............................................................................................................................. 119
6.2 Input/Output Pins ............................................................................................................... 121
6.3 Register Descriptions ......................................................................................................... 121
6.3.1 Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to IPR16) .... 123
6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 125
6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 126
6.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 127
6.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 127
6.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 129
Rev. 2.00 Sep. 07, 2007 Page xi of xxxii