SH7261 Datasheet, PDF (836/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
(2) Reception Using Interrupt Data Flow Control
Start
Release from reset,
define SSICR configuration bits.
Enable SSI module,
enable data interrupts,
enable error interrupts.
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Wait for interrupt from SSI.
Yes
SSI error interrupt?
No
Read data from receive data register.
Use SSI status register bits
to realign data
after underflow/overflow.
Yes
Receive more data?
No
Disable SSI module,
disable data interrupts,
disable error interrupts,
enable idle interrupt.
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module.
End
Figure 18.23 Reception Using Interrupt Data Flow Control
Rev. 2.00 Sep. 07, 2007 Page 804 of 1312
REJ09B0320-0200