SH7261 Datasheet, PDF (365/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit
Bit Name
23 to 17 
Initial
Value
All 0
16
DREQ
0
Section 11 Direct Memory Access Controller (DMAC)
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W DMA Request
This bit is used to check whether a DMA request is
currently present.
Furthermore, when the software trigger is selected
(DCTG = "000000") by the DMA request source
selection bits (DCTG), DMA requests operate through
this bit.
The value of this bit changes according to the state of
DMA request input to the DMAC regardless of the
settings of the DMAC module activation bit (DMST)
and DMA transfer enable bit (DEN). The conditions for
setting and clearing the bit are determined by the DMA
request source selection bits (DCTG) and input sense
mode selection bits (STRG) as described below.
(a) When software triggering is selected (DCTG =
"000000") by the DMA request source selection
bits (DCTG).
• Condition for setting to "1"
This bit is set to "1" when a "1" is written to it by
software, generating the DMA request.
• Condition for clearing to "0"
This bit is cleared to "0" by either of the below
events.
 Software writing a "0" to the bit
 The start of the transfer operation
corresponding to the bit setting
Rev. 2.00 Sep. 07, 2007 Page 333 of 1312
REJ09B0320-0200