SH7261 Datasheet, PDF (897/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.6.4 Message Receive Sequence
The diagram below shows the message receive sequence.
CAN Bus
RCAN-ET
End Of Arbitration Field
IDLE
End Of Frame
Valid CAN-ID Received
Loop (n = 15; n ≥ 0; n = n - 1)
n=n-1
Valid CAN Frame Received
Compare ID with
Mailbox[N] + LAFM[N]
(if MBC is config to receive)
Yes
No
ID Matched?
No
Yes
N = 0?
Yes
Store Mailbox-Number[N]
and go back to idle state
RXPR[N]
(RFPR[N])
Already Set?
No
Yes
OverWrite
• Store Message by Overwriting
• Set UMSR
• Set IRR9 (if MBIMR[N] = 0)
• Generate Interrupt Signal
(if IMR9 = 0)
• Set RXPR[N] (RFPR[N])
• Set IRR1 (IRR2) (if MBIMR[N] = 0)
• Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
Intrrupt signal
OverRun
• Reject Message
• Set UMSR
• Set IRR9 (if MBIMR[N] = 0)
• Generate Interrupt Signal
(if IMR9 = 0)
• Set RXPR[N] (RFPR[N])*1
Intrrupt signal
MSG
OverWrite or
OverRun?
(NMC)
• Store Message
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
Intrrupt signal
Exit Interrpt Service
Routine
Clear by clear
UMSR[N]*²
Clear by clear
UMSR[N]*²
Write 1 to RXPR[N] Write 1 to RFPR[N]
Read Mailbox[N]
Read Mailbox[N]
Read RXPR[N] = 1 Read RFPR[N] = 1
Yes
IRR[1]
No
set?
Read IRR
CPU received interrupt due to CAN Message Reception
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even thuotgh
the message has not been updated.
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N]
cleared and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/
RFPR[N]/UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Figure 19.11 Message receive sequence
Rev. 2.00 Sep. 07, 2007 Page 865 of 1312
REJ09B0320-0200