SH7261 Datasheet, PDF (539/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3 and TCNT_4 values
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
TGRA_4
Initial output
Complementary
PWM mode
(TMDR setting)
TCNT_3 and TCNT_4 count start
(TSTR setting)
Active level
Time
Figure 12.45 Example of Initial Output in Complementary PWM Mode (2)
Rev. 2.00 Sep. 07, 2007 Page 507 of 1312
REJ09B0320-0200