SH7261 Datasheet, PDF (119/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
4.4 Register Descriptions
The clock pulse generator has the following registers.
Table 4.4 Register Configuration
Register Name
Frequency control register
CKIO control register
Abbreviation R/W
FRQCR
R/W
CKIOCR
R/W
Initial Value Address Access Size
H'1003
H'FFFE0010 16
H'10/H'00 H'FFFE3894 8, 16, 32
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the
frequency division ratio of the internal clock and peripheral clock (Pφ). Only word access can be
used on FRQCR.
FRQCR is initialized to H'1003 only by a power-on reset or in deep standby mode. FRQCR retains
its previous value by a manual reset or in software standby mode. The previous value is also
retained when an internal reset is triggered by an overflow of the WDT.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — CKOEN —
STC[2:0]
—
IFC[2:0]
RNGS
PFC[2:0]
Initial value: 0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
R/W: R R R R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 13 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 87 of 1312
REJ09B0320-0200