SH7261 Datasheet, PDF (682/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Realtime Clock (RTC)
15.3.9 Second Alarm Register (RSECAR)
RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the
RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From
among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and
alarm register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
The assignable range is from 00 through 59 + ENB bits (practically in BCD), otherwise operation
errors occur.
The ENB bit in RSECAR is initialized to 0 by a power-on reset or in deep standby mode. The
other bits are not initialized by a power-on reset or manual reset, or in deep standby and software
standby modes.
Bit: 7
6
5
4
3
2
1
0
ENB
10 seconds
1 second
Initial value: 0 — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6 to 4
3 to 0
Initial
Bit Name Value
R/W
ENB
0
R/W
10 seconds Undefined R/W
1 second Undefined R/W
Description
When this bit is set to 1, a comparison with the
RSECCNT value is performed.
Ten's position of seconds setting value
One's position of seconds setting value
Rev. 2.00 Sep. 07, 2007 Page 650 of 1312
REJ09B0320-0200