SH7261 Datasheet, PDF (122/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
4.4.2 CKIO Control Register (CKIOCR)
CKIOCR is an 8-bit readable/writable register used to control output of the CKIO pin. When this
LSI is started in clock operating mode 3, writing 1 to this register is invalid.
When this LSI is started in clock operating mode 3, CKIOCR is initialized to H'00 by a power-on
reset caused by the RES pin or in deep standby mode. When this LSI is started in clock operating
mode 0 or 2, CKIOCR is initialized to H'01 by a power-on reset caused by the RES pin or in deep
standby mode. This register is not initialized by an internal reset triggered by an overflow of the
WDT, a manual reset, in sleep mode, or in software standby mode.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CKIO
OE
Initial value: 0
0
0
0
0
0
0 0/1*
R/W: R R R R R R R R/W
Initial
Bit
Bit Name Value R/W Description
7 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
CKIOOE 0/1*
R/W CKIO Output Enable
Enables output of the CKIO pin.
0: Output from CKIO is not enabled.
1: Output from CKIO is enabled.
Note: * The initial value depends on the clock operating mode of the LSI.
Rev. 2.00 Sep. 07, 2007 Page 90 of 1312
REJ09B0320-0200