SH7261 Datasheet, PDF (1019/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit Bit Name
3, 2 BUFEND1
[1:0]
1, 0 
Section 21 CD-ROM Decoder (ROM-DEC)
Initial
Value
10
All 0
R/W Description
R/W These bits select whether to change the order of 16-bit
units of data transferred from the SSI module or
suppress the stream data. In the SSI module, either
"padding mode" or "non-padding mode" is selectable. In
non-padding mode, each 32 bits of data transferred
from the SSI are CD-ROM data. Since the CD-ROM
decoder has two 16-bit input data registers, the order of
the 16-bit data can be swapped within the 32 bits. On
the other hand, in padding mode each 32 bits of data
transferred from the SSI includes padding. Since the
padding is without meaning, it should be kept out of the
input stream to the decoder. This suppression can be
specified by the setting of this register.
The CD-ROM decoder handles data as a stream of 16-
bit data, and this register controls which 16-bit portion of
each 32 bits of data transferred from the SSI should be
input second.
00: The 16 bits of stream data that would otherwise be
processed second is discarded.
01: The higher-order 16 bits of each 32 bits of data
received from the SSI are placed second in the
stream to the decoder.
10: The higher-order 16 bits of each 32 bits of data
received from the SSI are placed second in the
stream to the decoder.
11: Setting prohibited. If made, this setting will produce
a malfunction.
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 987 of 1312
REJ09B0320-0200