SH7261 Datasheet, PDF (1160/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.2.1 Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This
register is initialized to H'00 by a power-on reset or in deep standby mode but retains its previous
value by a manual reset or in software standby mode. Only byte access is valid.
Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7
6
5
4
3
2
1
0
STBY DEEP     MSTP1 
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R/W R
Initial
Bit
Bit Name Value R/W
7
STBY
0
R/W
6
DEEP
0
R/W
5 to 2 
All 0
R
1
MSTP1
0
R/W
0

0
R
[Legend]
x:
Don't care
Description
Software Standby, Deep Standby
Specifies transition to software standby mode or
deep standby mode.
0x: Executing SLEEP instruction puts chip into
sleep mode.
10: Executing SLEEP instruction puts chip into
software standby mode.
11: Executing SLEEP instruction puts chip into deep
standby mode.
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop 1
Setting the MSTP1 bit to 1 stops supplying clock to
RTC
0: RTC runs
1: Stops supplying clock to RTC
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1128 of 1312
REJ09B0320-0200